1. Field of the Invention
This invention is generally related to transistors for implementing switches.
2. Related Art
Transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are frequently used as switching elements in integrated circuits. Because transistor-based switches are easily controlled by an input voltage and are a relatively simple and low cost solution for high-speed switching, there are a variety of situations in which they are employed. For example, transistor-based switches may be used to implement the switched capacitor tank in a voltage-controlled oscillator (VCO): In fact, the types of applications in which transistor-based switches are currently being, or will be used, or nearly infinite.
Although transistor-based switches are relatively simple and cost-effective, there are significant challenges in designing the semiconductor characteristics of the transistor. In designing transistor-based switches, the nature of the inverse relationship between resistance and capacitance, makes it difficult to minimize the overall parasitic resistance of the transistor device, while also minimizing overall capacitance of the transistor device. For example, in prior art transistor-based switches, reducing the effective parasitic resistance of the transistor device disadvantageously produces a nearly equivalent increase in the effective parasitic capacitance. Furthermore, due to parasitic effects, prior art transistor-based switches are also problematic for numerous higher frequency applications.
The invention relates to systems for reducing and/or improving the parasitic effects of a transistor-based switch. In this regard, an embodiment of the invention is a transistor circuit for implementing a switch having reduced parasitic effects. In general, the transistor circuit comprises a first switch node, a second switch node, a third switch node, a transistor device, and a circuit configured to reduce the parasitic characteristics of the transistor device. The first switch node is configured to connect to one node of an external circuit. The second switch node is configured to connect to a second node of the external circuit. The transistor device is a three-terminal device. The first terminal is connected to the first switch node. The second terminal is connected to the second switch node. The third terminal is for receiving a control signal that operates the transistor circuit as a switch by controlling the electrical connectivity between the first terminal and the second terminal. The third switch node is configured to receive the control signal.
Another transistor circuit for implementing a switch having reduced parasitic effects comprises a first switch node, a second switch node, a transistor device, and an inverter circuit. The first switch node is configured to connect to one node of an external circuit. The second switch node is configured to connect to a second node of the external circuit. The transistor device is a three-terminal device. The first terminal is connected to the first switch node. The second terminal is connected to the second switch node. The inverter circuit is connected to the second terminal of the transistor device and is configured to provide a voltage to the second terminal when the control signal engages the transistor device.
The invention also provides a transistor circuit for implementing a switch having improved parasitic effects. The transistor circuit comprises a first switch node, a second switch node, a first transistor device, a second transistor device, and a third transistor device. The first switch node is configured to connect to one node in an external circuit. The second switch node is configured to connect to another node in the external circuit. The first, second, and third transistor devices are three-terminal devices. A first terminal of the first transistor device is connected to the first switch node. A third terminal of the first transistor device is configured to receive a control signal that controls the electrical connectivity between the first terminal and the second terminal. A first terminal of the second transistor device is connected to the third terminal of the first transistor device. A second terminal of the second transistor device is connected to the second switch node. A third terminal of the second transistor is configured to receive the control signal. A first terminal of the third transistor device is connected to the first terminal of the first transistor device. A second terminal of the third transistor device is connected to a second terminal of the second transistor device. A third terminal of the third transistor device is configured to receive the control signal. Importantly, the first transistor, the second transistor, and the third transistor may be configured in a predetermined manner so that the parasitic characteristics of the first transistor, the second transistor, and the third transistor result in the transistor circuit having improved parasitic characteristics.
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.